Typically, the heart of a personal computer system is a central processing unit (CPU) that resides on a microprocessor chip. New microprocessor chips that operate at increasingly high operating speeds are constantly being developed in order to permit personal computers to execute large programs and process large data files in a timely manner.
If the next instruction to be executed is not available when the microprocessor needs it, then the microprocessor typically must wait idly (i.e. insert wait cycles) while the required instruction is retrieved and provided to the microprocessor. Furthermore, if the next instruction to be executed requires data that is not immediately available to the microprocessor, the microprocessor must also idle until the data has been retrieved. Therefore, many modern high performance microprocessors have an internal cache. Instructions that are likely to be executed, and data that are likely to be needed by the executing instructions, are stored in the internal cache so that they may be accessed immediately by the CPU of the microprocessor.
Because the internal cache is typically filled a cache line at a time, many microprocessors can accept data in a burst mode. In a typical burst read, the microprocessor specifies the addresses of the data or instructions to be read into a cache line. Then, the data or instructions that are stored at the specified addresses are sent from where they are stored within the computer system to the microprocessor. Alternately, the microprocessor specifies a single address of the cache line, then the addresses of the rest of the cache line are calculated and the data at these locations are sent to the microprocessor.
Typically, an address is specified as a single monolithic address and each bit of the address is specified on its own address bit line. An address valid signal is provided with the address to signify that a valid address is being asserted on the address lines. Alternately, the number of address lines can be reduced by dividing an address into parts and then multiplexing the address parts on the address lines. For example, a single address can map into a row and column address pair. The row and column addresses then share the same set of address lines. Typically, row and column address strobe signals are provided to indicate respectively when a valid row or column address is placed on the shared address lines.
A high speed microprocessor chip typically interfaces with the rest of the computer system using at least one high speed bus to access fast (low latency) devices. Examples of devices that typically are coupled to the high speed bus include the main memory of the computer system and an external memory cache.
A computer system also typically has a relatively low speed bus to access slow (high latency) devices. Some microprocessor can interface directly with the low speed bus. Alternately, the low speed bus is coupled to the high speed bus using a bus bridge. One type of device that is typically coupled to the low speed bus uses flash memory. Flash memory typically is a high-density, nonvolatile, read-write memory. Examples of flash memory based devices include BIOS ROM and hard disk substitutes. The read operation associated with a typical flash memory array closely resembles the read operation associated with other read-only memory devices. Write and erase operations for a flash memory array are, however, significantly slower than the read operation.
British patent document no. GB 2 251 324 A, published Jul. 1, 1992, describes a computer system that uses flash memory. The patent document discloses various architectures to incorporate a flash memory into a computer system. One architecture referred to therein is a variable file structure. For the variable file structure, computer code is stored contiguously in flash memory, allowing a CPU to execute computer code directly from the flash memory array without the need for RAM.
Thus, flash memory can serve as the main memory within computers, providing user functions similar to those of disk-based systems. For example, by storing application software and operating system code in a Resident Flash Array (RFA), users enjoy virtually instant-on performance and in-place code execution. An RFA also protects against software obsolescence because, unlike ROM, it is in-system updatable. Resident software, stored in flash rather than disk, extends battery life and increases system reliability. File management software such as Microsoft's Flash File System (FFS) allows flash memory components and flash cards to emulate the file storage capabilities of disk thereby making the management of flash memory devices completely transparent to the user.
During a typical read operation for a flash memory device, an address corresponding to a location within the device to be read is sent to the device. The address is then decoded into a row and column address pair. This row and column address pair corresponds to a set of flash memory cells within a flash memory array that contain the data stored at the address to be read. These cells are then sensed to determine the value of the data stored within them. Finally, the data that has been sensed is output from the flash device.
Address transition detection ("ATD") is also well known in the art and has been widely used in memory devices. The purpose of address transition detection circuitry is to increase the speed with which data can be read from memory. This is accomplished by performing operations that are required for every memory read operation as soon as an address transition has been detected.
These operations include equalizing sense amplifiers and latching the previous output. The sense amplifiers are used to increase weak signals sensed from the memory cells to be read during the read operation. Equalizing the sense amplifiers causes the amplifiers to be cleared or otherwise set up so that they are ready to process the new data to be read. Latching the previous output causes the output to remain static until the new data from the read operation has been output from the sense amplifiers. The previous output is latched because the output of the sense amplifiers fluctuates before it finally reaches a steady value. Latching the previous output ensures that the swing does not pass down to the outputs. Circuitry to equalize the sense amplifiers and latch previous output is well known in the art.
Flash memory typically has an asynchronous interface wherein an address to be read is specified and then, a set time later, the contents stored at the specified address are output from the flash chip. It is only after the data has been output from the flash chip that the next address to be read can be sent to the flash chip. A high speed bus can run at 33 MHz wherein every cycle of the bus takes about 30 nanoseconds (nS). A typical high speed flash chip, on the other hand, has a read access time of about 80 nS. Hence, if flash memory is to be used as main memory, every single memory access to flash involves wait states and zero wait state back to back burst cycles from flash cannot be supported. This is true for other devices having a read latency similar to that of flash memory. Thus, using prior art technology, it is not practical to use these memories as main memory for a high speed microprocessor.